In recent years, sigma delta modulation has gained increasing significance in the field of analog/digital (A/D) and digital/analog (D/A) conversion. This is mainly attributable to the low requirements for the analog components of signal converters. Digital circuits are gaining more and more significance in present day signal processing. To be able to convert the signals from the analog environment and then to be able to process them digitally, A/D converters are necessary. It is desirable to integrate converters and the remaining digital circuit on a single chip. Since the digital proportion in most cases dominates the chip area, it also determines the circuit technology. However, digital process technologies make it difficult to produce precise analog integrated circuit components in which very high accuracies and little manufacturing variation are demanded. This is where the simplicity and ruggedness of analog components of the sigma delta modulators become important, which predestine the sigma delta converters for implementations in, for example, digital VLSI technology.
A further advantage of the sigma delta modulators lies in the fact that they need less current than the conventional A/D converters, which also qualifies them in the important field of portable receivers. Similarly, they are distinguished by a higher signal bandwidth, which makes them interesting for application in xDSL transceiver technology.
The problem with sigma delta modulators is that errors occur due to propagation delays in the individual components (excess loop delay), especially toward higher frequencies to be converted, which limits their application to high frequencies (>1 GHz). With regard to the problems of excess loop delays, see also J. A. Cherry, W. M. Snelgrove, Continuous-Time Delta Sigma Modulator for High Speed A/D Conversion, Kluwer Academic Publishers 2000, pages 75-103.
A known approach to compensate for these errors induced by delay differences is the approach, known from P. Benabes, M. Keramat, R. Kielbasa, A methodology for designing continuous-time sigma-delta modulators, IEEE European Design and Test Conference 1997, pages 45-50, of introducing an additional feedback circuit (inner loop) which is formed by an additional adder between the quantizer and the last integrator preceding it.
FIG. 1 shows a conventional continuous-time second order sigma delta modulator with two preliminary stages V1 and V2 and with correction means. The signal x to be converted, which is present at the input IN, is supplied to the quantizer 2 at its input EQ via two integrators 41 and 42, each of which is in each case preceded by an adder 31 and 32, respectively, to link up with the feedback signal. Before that, however, the signal to be quantized is again combined with the feedback signal via the adder 10. This takes into consideration and compensates for the influence of the delay in the individual components.
FIG. 2 shows a possible conversion of such a concept known from W. Redman-White, A. M. Durham, A fourth order Converter with self-tuning Continuous Time Noise Shaper, from Proceedings of ESSCIRC 1991, pages 249-252.
In this concept, current AD converters 61 to 62 are used as digital/analog converters for the feedback signal Ri, the integrators 41 and 42 being formed by operational amplifiers and the compensation adder 10 also being constructed by an operational amplifier preceded by a current AD converter 63. In this solution, the summing nodes 3i are formed by the inputs of the operational amplifiers. The summing signals are the currents which flow through the input resistors and into the current generators in the respective feedback circuit.
FIG. 3 shows a diagram of a three-bit resolution sigma delta modulator constructed in this way in which seven threshold voltages are used.
According to the arrangement specified above, the sum is formed with the feedback signal before the quantizer. The comparators i=1 to N of the quantizer, therefore, must perform the weighting(V2−Vdac3)>Vth,i(see also FIG. 4) where V2 is the amount of the intermediate signal y2 after the second integrator 42.
The disadvantageous factor in this arrangement and procedure is, however, that a highly accurate active element (additional adder) must be provided in the signal path, with all the problems with regard to manufacturing methods and steps, layout design and waste in the manufacturing, and that the current consumption is considerably increased by this, which limits the fields of application especially in the case of portable applications which require current saving.